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3.6 Support Components
Figure 3.4
LSIFC929 Typical Implementation
2
FC
2
Channel 0
2
FC
2
Channel 1
Clock
(106 MHz)
3.6.1 SSRAM Memory
3-8
The memory controller block within the LSIFC929 provides access to
external local memory resources required to manage FCP.
The following sections provide guidance in choosing the support
components necessary for a fully functional implementation using the
LSIFC929. A LSIFC929 typical implementation diagram is shown below
in
Figure 3.4
for reference.
Integrated
Transceiver
Integrated
Transceiver
SSRAM
(1 Mbyte typ.)
The primary function of this memory is to store data structures used by
the LSIFC929 to manage exchanges and transmit and receive queues.
The SSRAM memory also stores part of the run time image of the
LSIFC929 firmware, such as initialization and error recovery code. The
mainline code is stored within the internal LRAM for performance
reasons.
The LSIFC929 uses a 32 bit nonmultiplexed memory bus to access the
SSRAM. This memory bus has the capability to address up to 4 Mbytes
of SSRAM.
LSIFC929 Overview
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
LSIFC929
Memory
Controller
32
Serial
Flash
EEPROM
(1 Mbyte)
(2 Kbyte)
PCI Bus
32/64
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