Lsi53C875A Host Interface Scsi Data Paths - LSI LSI53C875A Technical Manual

Figure 2.4

LSI53C875A Host Interface SCSI Data Paths

Asynchronous
SCSI Send
PCI Interface**
DMA FIFO*
(8 Bytes x 118)
SODL Register*
SCSI Interface**
Asynchronous
SCSI Receive
PCI Interface**
DMA FIFO*
(8 Bytes x 118)
SWIDE Register
SIDL Register*
SCSI Interface**
The following steps determine if any bytes remain in the data path when
the chip halts an operation:
Asynchronous SCSI Send –
Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the
Five (CTEST5)
(DFIFO) and
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between zero and 112.
If the DMA FIFO size is set to 944 bytes (bit 5 of the
Five (CTEST5)
SCSI Functional Description
Synchronous
SCSI Send
PCI Interface**
DMA FIFO*
(8 Bytes x 118)
SODL Register*
SODR Register*
SCSI Interface**
register cleared), look at the
DMA Byte Counter (DBC)
register is set), subtract the 10 least significant
Synchronous
SCSI Receive
PCI Interface**
DMA FIFO*
(8 Bytes x 118)
SWIDE Register
SCSI FIFO**
(1 or 2 Bytes x 31)
SCSI Interface**
* = No parity protection
** = Parity protected
Chip Test
DMA FIFO
registers and calculate
Chip Test
2-29