Register Descriptions; C Bus Control Register 1 (Iccr1) - Renesas H8 Series Hardware Manual

2
Section 15 I C Bus Interface 2 (IIC2)
15.3

Register Descriptions

2
The I C bus interface 2 has the following registers:
• I
2

C bus control register 1 (ICCR1)

• I
2
C bus control register 2 (ICCR2)
• I
2
C bus mode register (ICMR)
• I
2
C bus interrupt enable register (ICIER)
• I
2
C bus status register (ICSR)
• I
2
C bus slave address register (SAR)
• I
2
C bus transmit data register (ICDRT)
• I
2
C bus receive data register (ICDRR)
• I
2
C bus shift register (ICDRS)
2
15.3.1 I C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit Bit Name
7 ICE
6 RCVD
Rev. 1.00 Aug. 28, 2006 Page 244 of 400
REJ09B0268-0100
2
C bus interface 2, controls transmission or reception, and selects
Initial
Value R/W Description
2
0 R/W I C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to port
function.)
1: This bit is enabled for transfer operations. (SCL and SDA
pins are bus drive state.)
0 R/W Reception Disable
This bit enables or disables the next operation when TRS is
0 and ICDRR is read.
0: Enables next reception
1: Disables next reception