Renesas H8 Series Hardware Manual page 21

Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/36094 Group of F-ZTAT
Figure 1.2 Pin Assignments of H8/36094 Group of F-ZTAT
Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTAT
Section 2 CPU
Figure 2.1 Memory map ............................................................................................................... 10
Figure 2.2 CPU Registers ............................................................................................................. 11
Figure 2.3 Usage of General Registers ......................................................................................... 12
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 13
Figure 2.5 General Register Data Formats (1).............................................................................. 15
Figure 2.5 General Register Data Formats (2).............................................................................. 16
Figure 2.6 Memory Data Formats................................................................................................. 17
Figure 2.7 Instruction Formats...................................................................................................... 28
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 31
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 34
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 35
Figure 2.11 CPU Operation States................................................................................................ 36
Figure 2.12 State Transitions ........................................................................................................ 37
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address...................................................................................................................... 38
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 52
Figure 3.2 Stack Status after Exception Handling ........................................................................ 54
Figure 3.3 Interrupt Sequence....................................................................................................... 55
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 56
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 57
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 61
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 61
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 63
Figure 5.2 State Transition of System Clock ................................................................................ 70
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 71
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)
(From On-Chip Oscillator Clock to External Clock) ................................................ 72
Figures
TM
(FP-64K, FP-64A) ...................... 4
TM
(FP-48F, FP-48B, TNP-48) ........ 5
Rev. 1.00 Aug. 28, 2006 Page xix of xxviii
TM
.......................................... 3