Renesas H8 Series Hardware Manual page 391

16-bit single-chip microcomputer
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Instruction Mnemonic
BIOR
BIOR #xx:8, Rd
BIOR #xx:8, @ERd
BIOR #xx:8, @aa:8
BIST
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
BIXOR
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
BLD
BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
BNOT
BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
BOR
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
BSET
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
BSR
BSR d:8
BSR d:16
BST
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
Instruction
Branch
Fetch
Addr. Read
I
J
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
2
2
1
2
2
Stack
Byte Data
Operation
Access
K
L
1
1
2
2
1
1
1
1
2
2
2
2
1
1
2
2
2
2
1
1
2
2
Rev. 1.00 Aug. 28, 2006 Page 361 of 400
Appendix
Word Data
Internal
Access
Operation
M
N
2
REJ09B0268-0100

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