Renesas H8 Series Hardware Manual page 74

Section 3 Exception Handling
Relative Module
CPU
External interrupt
pin
Timer A

Timer W
Timer V
SCI3
IIC2
A/D converter

Clock switching
Note * A low-voltage detection interrupt is enabled only in the product with an on-chip power-
on reset and low-voltage detection circuit.
Rev. 1.00 Aug. 28, 2006 Page 44 of 400
REJ09B0268-0100
Exception Sources
Direct transition by executing the
SLEEP instruction
IRQ0
Low-voltage detection interrupt*
IRQ1
IRQ2
IRQ3
WKP
Overflow
Reserved for system use
Timer W input capture A/
compare match A
Timer W input capture B/
compare match B
Timer W input capture C/
compare match C
Timer W input capture D/
compare match D
Timer W overflow
Timer V compare match A
Timer V compare match B
Timer V overflow
SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
Transmit data empty
Transmit end
Receive data full
Arbitration lost/Overrun error
NACK detection
Stop conditions detected
A/D conversion end
Reserved for system use
Clock switching
(from external clock to on-chip
oscillator clock)
Vector
Number Vector Address
13 H'001A to H'001B
14 H'001C to H'001D
15 H'001E to H'001F
16 H'0020 to H'0021
17 H'0022 to H'0023
18 H'0024 to H'0025
19 H'0026 to H'0027
20 H'0028 to H'0029
21 H'002A to H'002B
22 H'002C to H'002D
23 H'002E to H'002F
24 H'0030 to H'0031
25 H'0032 to H'0033
26 to 33 H'0034 to H'0043
34 H'0044 to H'0045
Priority
High
Low