Port 5; Figure 9.3 Port 5 Pin Configuration - Renesas H8 Series Hardware Manual

• P20/SCK3 pin
Register
Bit Name CKE1
Setting Value 0
0
0
1
Legend X: Don't care.
9.3

Port 5

Port 5 is a general I/O port also functioning as an I
pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting
2
of the I C bus interface register has priority for functions of the pins P57/SCL and P56/SDA. Since
the output buffer for pins P56 and P57 has the NMOS push-pull structure, it differs from an output
buffer with the CMOS structure in the high-level output characteristics (see section 20, Electrical
Characteristics).
SCR3 SMR
CKE0 COM
0 0
0 1
1 X
X X
Port 5

Figure 9.3 Port 5 Pin Configuration

PCR2
PCR20
0
1
X
X
X
2
C bus interface I/O pin, an A/D trigger input
P57/SCL
P56/SDA
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
Rev. 1.00 Aug. 28, 2006 Page 125 of 400
Section 9 I/O Ports
Pin Function
P20 input pin
P20 output pin
SCK3 output pin
SCK3 output pin
SCK3 input pin
REJ09B0268-0100