Renesas H8 Series Hardware Manual page 27

Section 1 Overview
Table 1.1 Pin Functions ............................................................................................................ 6
Section 2 CPU
Table 2.1 Operation Notation ................................................................................................. 18
Table 2.2 Data Transfer Instructions....................................................................................... 19
Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 20
Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 21
Table 2.4 Logic Operations Instructions................................................................................. 22
Table 2.5 Shift Instructions..................................................................................................... 22
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 23
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 24
Table 2.7 Branch Instructions ................................................................................................. 25
Table 2.8 System Control Instructions.................................................................................... 26
Table 2.9 Block Data Transfer Instructions ............................................................................ 27
Table 2.10 Addressing Modes .................................................................................................. 29
Table 2.11 Absolute Address Access Ranges ........................................................................... 30
Table 2.12 Effective Address Calculation (1)........................................................................... 32
Table 2.12 Effective Address Calculation (2)........................................................................... 33
Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address .................................................................. 43
Table 3.2 Interrupt Wait States ............................................................................................... 54
Section 4 Address Break
Table 4.1 Access and Data Bus Used ..................................................................................... 59
Section 5 Clock Pulse Generators
Table 5.1 Crystal Resonator Parameters ................................................................................. 79
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Waiting Time................................................................. 87
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 90
Table 6.3 Internal State in Each Operating Mode................................................................... 91
Section 7 ROM
Table 7.1 Setting Programming Modes ................................................................................ 103
Table 7.2 Boot Mode Operation ........................................................................................... 105
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible ................................................................................................................. 106
Tables
Rev. 1.00 Aug. 28, 2006 Page xxv of xxviii