Table A.3 Number Of Cycles In Each Instruction - Renesas H8 Series Hardware Manual

Appendix
Table A.3 Number of Cycles in Each Instruction
Execution Status
(Instruction Cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note: * Depends on which on-chip peripheral module is accessed. See section 19.1, Register
Addresses (Address Order).
Rev. 1.00 Aug. 28, 2006 Page 358 of 400
REJ09B0268-0100
On-Chip Memory
S 2
I
S
J
S
K
S
L
S
M
S
N
Access Location
On-Chip Peripheral Module
—
2 or 3*
2 or 3*
1