Operation; Figure 13.2 Watchdog Timer Operation Example - Renesas H8 Series Hardware Manual

13.3

Operation

The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to
B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate
the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input
after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset
signal is generated. The internal reset signal is output for a period of 256 φ
is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An
overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the
TCWD set value.
Figure 13.2 shows an example of watchdog timer operation.
With 30ms overflow period when φ = 4 MHz
Example:
4 × 10
8192
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
H'FF
TCWD
count value
H'00
Internal reset
signal
6
× 30 × 10 –3
= 14.6
H'F1
Start
H'F1 written H'F1 written to TCWD
to TCWD

Figure 13.2 Watchdog Timer Operation Example

Section 13 Watchdog Timer
clock cycles. TCWD
osc
TCWD overflow
Reset generated
256 φ
clock cycles
osc
Rev. 1.00 Aug. 28, 2006 Page 199 of 400
REJ09B0268-0100