Renesas H8 Series Hardware Manual page 25

Figure 15.8 Master Receive Mode Operation Timing (2)........................................................... 262
Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 263
Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 264
Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 265
Figure 15.12 Slave Receive Mode Operation Timing (2)........................................................... 265
Figure 15.13 Clocked Synchronous Serial Transfer Format....................................................... 266
Figure 15.14 Transmit Mode Operation Timing......................................................................... 267
Figure 15.15 Receive Mode Operation Timing .......................................................................... 268
Figure 15.16 Block Diagram of Noise Conceler......................................................................... 268
Figure 15.17 Sample Flowchart for Master Transmit Mode....................................................... 269
Figure 15.18 Sample Flowchart for Master Receive Mode ........................................................ 270
Figure 15.19 Sample Flowchart for Slave Transmit Mode......................................................... 271
Figure 15.20 Sample Flowchart for Slave Receive Mode .......................................................... 272
Figure 15.21 The Timing of the Bit Synchronous Circuit .......................................................... 274
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................... 276
Figure 16.2 A/D Conversion Timing .......................................................................................... 283
Figure 16.3 External Trigger Input Timing ................................................................................ 284
Figure 16.4 A/D Conversion Accuracy Definitions (1) .............................................................. 286
Figure 16.5 A/D Conversion Accuracy Definitions (2) .............................................................. 286
Figure 16.6 Analog Input Circuit Example................................................................................. 287
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
Figure 17.1 Block Diagram around BGR ................................................................................... 290
Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 291
Figure 17.3 Operational Timing of Power-On Reset Circuit...................................................... 296
Figure 17.4 Operating Timing of LVDR Circuit ........................................................................ 297
Figure 17.5 Operational Timing of LVDI Circuit....................................................................... 298
Figure 17.6 Timing of Setting Bits in Reset Source Decision Register...................................... 299
Section 18 Power Supply Circuit
Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 301
Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 302
Section 20 Electrical Characteristics
Figure 20.1 System Clock Input Timing..................................................................................... 335
Figure 20.2 RES Low Width Timing.......................................................................................... 335
Figure 20.3 Input Timing............................................................................................................ 335
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Figure 20.4 I C Bus Interface Input/Output Timing ................................................................... 336
Figure 20.5 SCK3 Input Clock Timing....................................................................................... 336
Figure 20.6 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 337
Rev. 1.00 Aug. 28, 2006 Page xxiii of xxviii