Erase/Erase-Verify; Table 7.4 Reprogram Data Computation Table; Table 7.5 Additional-Program Data Computation Table; Table 7.6 Programming Time - Renesas H8 Series Hardware Manual

Table 7.4 Reprogram Data Computation Table
Program Data
0
0
1
1
Table 7.5 Additional-Program Data Computation Table
Reprogram Data
0
0
1
1
Table 7.6 Programming Time
n
(Number of Writes)
1 to 6
7 to 1,000
Note: Time shown in µs.
7.4.2

Erase/Erase-Verify

When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
Verify Data
0
1
0
1
Verify Data
0
1
0
1
Programming
Time
30
200
Reprogram Data
1
0
1
1
Additional-Program
Data
0
1
1
1
In Additional
Programming
10
—
Rev. 1.00 Aug. 28, 2006 Page 109 of 400
Section 7 ROM
Comments
Programming completed
Reprogram bit
—
Remains in erased state
Comments
Additional-program bit
No additional programming
No additional programming
No additional programming
Comments
REJ09B0268-0100