Figure 15.1 Block Diagram Of I - Renesas H8 Series Hardware Manual

16-bit single-chip microcomputer
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2
Section 15 I
C Bus Interface 2 (IIC2)
Output
SCL
control
Noise canceler
Output
SDA
control
Noise canceler
[Legend]
ICCR1 :
ICCR2 :
ICMR :
ICSR :
ICIER :
ICDRT :
ICDRR :
ICDRS :
SAR :
Rev. 1.00 Aug. 28, 2006 Page 242 of 400
REJ09B0268-0100
Transmission/
Bus state
decision circuit
Arbitration
decision circuit
2
I
C bus control register 1
2
I
C bus control register 2
2
I
C bus mode register
2
I
C bus status register
2
I
C bus interrupt enable register
2
I
C bus transmit data register
2
I
C bus receive data register
2
I
C bus shift register
Slave address register

Figure 15.1 Block Diagram of I

reception
control circuit
ICDRT
ICDRS
ICDRR
ICIER
2
C Bus Interface 2
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Address
comparator
ICSR
Interrupt
Interrupt request
generator

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