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Renesas H8/36094 Series Manuals
Manuals and User Guides for Renesas H8/36094 Series. We have
1
Renesas H8/36094 Series manual available for free PDF download: Hardware Manual
Renesas H8/36094 Series Hardware Manual (434 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 2.67 MB
Table of Contents
General Precautions on Handling of Product
6
Preface
8
Table of Contents
11
Section 1 Overview
31
Features
31
Section 1 Overview
32
Internal Block Diagram
33
Figure 1.1 Internal Block Diagram of H8/36094 Group of F-ZTAT TM
33
Pin Assignments
34
Figure 1.2 Pin Assignments of H8/36094 Group of F-ZTAT TM (FP-64K, FP-64A)
34
Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTAT TM (FP-48F, FP-48B, TNP-48)
35
Overview
35
Pin Functions
36
Table 1.1 Pin Functions
36
Section 2 CPU
39
Address Space and Memory Map
40
Figure 2.1 Memory Map
40
Register Configuration
41
Figure 2.2 CPU Registers
41
Figure 2.3 Usage of General Registers
42
General Registers
42
Appendix
43
Condition-Code Register (CCR)
43
Figure 2.4 Relationship between Stack Pointer and Stack Area
43
Program Counter (PC)
43
Data Formats
45
General Register Data Formats
45
Figure 2.5 General Register Data Formats (1)
45
Figure 2.5 General Register Data Formats (2)
46
Memory Data Formats
47
Figure 2.6 Memory Data Formats
47
Instruction Set
48
Table of Instructions Classified by Function
48
Table 2.1 Operation Notation
48
Table 2.2 Data Transfer Instructions
49
Table 2.3 Arithmetic Operations Instructions (1)
50
Table 2.3 Arithmetic Operations Instructions (2)
51
Table 2.4 Logic Operations Instructions
52
Table 2.5 Shift Instructions
52
Table 2.6 Bit Manipulation Instructions (1)
53
Table 2.6 Bit Manipulation Instructions (2)
54
Table 2.7 Branch Instructions
55
Table 2.8 System Control Instructions
56
Basic Instruction Formats
57
Table 2.9 Block Data Transfer Instructions
57
Addressing Modes and Effective Address Calculation
58
Addressing Modes
58
Figure 2.7 Instruction Formats
58
Table 2.10 Addressing Modes
59
Table 2.11 Absolute Address Access Ranges
60
Figure 2.8 Branch Address Specification in Memory Indirect Mode
61
Effective Address Calculation
62
Table 2.12 Effective Address Calculation (1)
62
Table 2.12 Effective Address Calculation (2)
63
Basic Bus Cycle
64
Access to On-Chip Memory (RAM, ROM)
64
Figure 2.9 On-Chip Memory Access Cycle
64
On-Chip Peripheral Modules
65
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
65
CPU States
66
Figure 2.11 CPU Operation States
66
Usage Notes
67
Notes on Data Access to Empty Areas
67
EEPMOV Instruction
67
Bit Manipulation Instruction
67
Figure 2.12 State Transitions
67
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to same
68
Section 3 Exception Handling
73
Exception Sources and Vector Address
73
Table 3.1 Exception Sources and Vector Address
73
Register Descriptions
75
Interrupt Edge Select Register 1 (IEGR1)
75
Interrupt Edge Select Register 2 (IEGR2)
76
Interrupt Enable Register 1 (IENR1)
77
Interrupt Flag Register 1 (IRR1)
78
Wakeup Interrupt Flag Register (IWPR)
79
Reset Exception Handling
81
Interrupt Exception Handling
81
External Interrupts
81
Figure 3.1 Reset Sequence
82
Internal Interrupts
83
Interrupt Handling Sequence
83
Interrupt Response Time
84
Figure 3.2 Stack Status after Exception Handling
84
Table 3.2 Interrupt Wait States
84
Figure 3.3 Interrupt Sequence
85
Usage Notes
86
Interrupts after Reset
86
Notes on Stack Area Use
86
Notes on Rewriting Port Mode Registers
86
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
86
Section 4 Address Break
87
Register Descriptions
87
Figure 4.1 Block Diagram of Address Break
87
Address Break Control Register (ABRKCR)
88
Address Break Status Register (ABRKSR)
89
Table 4.1 Access and Data Bus Used
89
Break Address Registers (BARH, BARL)
90
Break Data Registers (BDRH, BDRL)
90
Operation
90
Figure 4.2 Address Break Interrupt Operation Example (1)
91
Figure 4.2 Address Break Interrupt Operation Example (2)
91
Section 5 Clock Pulse Generators
93
Figure 5.1 Block Diagram of Clock Pulse Generators
93
Features
94
Register Descriptions
94
RC Control Register (RCCR)
95
RC Trimming Data Protect Register (RCTRMDPR)
96
RC Trimming Data Register (RCTRMDR)
97
Clock Control/Status Register (CKCSR)
98
System Clock Select Operation
100
Figure 5.2 State Transition of System Clock
100
Clock Control Operation
101
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled
101
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1) (from On-Chip Oscillator Clock to External Clock)
102
Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (from External Clock to On-Chip Oscillator Clock)
103
Clock Switching Timing
104
Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock
104
Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock
105
Figure 5.8 External Oscillation Backup Timing
106
Trimming of On-Chip Oscillator Frequency
107
Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock
107
Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency
108
External Clock Oscillators
109
Connecting Crystal Resonator
109
Figure 5.11 Example of Connection to Crystal Resonator
109
Figure 5.12 Equivalent Circuit of Crystal Resonator
109
Table 5.1 Crystal Resonator Parameters
109
Connecting Ceramic Resonator
110
Inputting External Clock
110
Figure 5.13 Example of Connection to Ceramic Resonator
110
Figure 5.14 Example of External Clock Input
110
Subclock Oscillator
111
Connecting 32.768-Khz Crystal Resonator
111
Figure 5.15 Block Diagram of Subclock Oscillator
111
Figure 5.16 Typical Connection to 32.768-Khz Crystal Resonator
111
Figure 5.17 Equivalent Circuit of 32.768-Khz Crystal Resonator
111
Pin Connection When Not Using Subclock
112
Prescaler
112
Prescaler S
112
Prescaler W
112
Figure 5.18 Pin Connection When Not Using Subclock
112
Usage Notes
113
Note on Resonators
113
Notes on Board Design
113
Figure 5.19 Example of Incorrect Board Design
113
Section 6 Power-Down Modes
115
Register Descriptions
115
System Control Register 1 (SYSCR1)
115
System Control Register 2 (SYSCR2)
117
Table 6.1 Operating Frequency and Waiting Time
117
Module Standby Control Register 1 (MSTCR1)
118
Mode Transitions and States of LSI
119
Figure 6.1 Mode Transition Diagram
119
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
120
Table 6.3 Internal State in each Operating Mode
121
Sleep Mode
122
Standby Mode
122
Subactive Mode
123
Subsleep Mode
123
Operating Frequency in Active Mode
124
Direct Transition
124
Direct Transition from Active Mode to Subactive Mode
124
Direct Transition from Subactive Mode to Active Mode
125
Module Standby Function
125
Section 7 ROM
127
Block Configuration
128
Figure 7.1 Flash Memory Block Configuration
128
Register Descriptions
129
Flash Memory Control Register 1 (FLMCR1)
129
Flash Memory Control Register 2 (FLMCR2)
130
Erase Block Register 1 (EBR1)
131
Flash Memory Power Control Register (FLPWCR)
132
Flash Memory Enable Register (FENR)
132
On-Board Programming Modes
133
Boot Mode
133
Table 7.1 Setting Programming Modes
133
Table 7.2 Boot Mode Operation
135
Programming/Erasing in User Program Mode
136
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
136
Table 7.3 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is Possible
136
Flash Memory Programming/Erasing
137
Program/Program-Verify
137
Figure 7.3 Program/Program-Verify Flowchart
138
Erase/Erase-Verify
139
Table 7.4 Reprogram Data Computation Table
139
Table 7.5 Additional-Program Data Computation Table
139
Table 7.6 Programming Time
139
Interrupt Handling When Programming/Erasing Flash Memory
140
Figure 7.4 Erase/Erase-Verify Flowchart
141
Program/Erase Protection
142
Hardware Protection
142
Software Protection
142
Error Protection
142
Programmer Mode
143
Power-Down States for Flash Memory
143
Table 7.7 Flash Memory Operating States
143
Section 8 RAM
145
Section 9 I/O Ports
147
Port 1
147
Figure 9.1 Port 1 Pin Configuration
147
Port Mode Register 1 (PMR1)
148
Port Control Register 1 (PCR1)
149
Port Data Register 1 (PDR1)
150
Port Pull-Up Control Register 1 (PUCR1)
150
Pin Functions
151
Port 2
153
Port Control Register 2 (PCR2)
153
Figure 9.2 Port 2 Pin Configuration
153
Port Data Register 2 (PDR2)
154
Pin Functions
154
Port 5
155
Figure 9.3 Port 5 Pin Configuration
155
Port Mode Register 5 (PMR5)
156
Port Control Register 5 (PCR5)
157
Port Data Register 5 (PDR5)
158
Port Pull-Up Control Register 5 (PUCR5)
158
Pin Functions
159
Port 7
161
Figure 9.4 Port 7 Pin Configuration
161
Port Control Register 7 (PCR7)
162
Port Data Register 7 (PDR7)
162
Pin Functions
163
Port 8
164
Figure 9.5 Port 8 Pin Configuration
164
Port Control Register 8 (PCR8)
165
Port Data Register 8 (PDR8)
165
Pin Functions
166
Port B
169
Port Data Register B (PDRB)
169
Figure 9.6 Port B Pin Configuration
169
Port C
170
Port Control Register C (PCRC)
170
Figure 9.7 Port C Pin Configuration
170
Port Data Register C (PDRC)
171
Pin Functions
171
Section 10 Timer a
173
Features
173
Input/Output Pins
174
Figure 10.1 Block Diagram of Timer a
174
Table 10.1 Pin Configuration
174
Register Descriptions
175
Timer Mode Register a (TMA)
175
Timer Counter a (TCA)
176
Operation
177
Interval Timer Operation
177
Clock Time Base Operation
177
Clock Output
177
Usage Note
177
Section 11 Timer V
179
Features
179
Input/Output Pins
181
Register Descriptions
181
Timer Counter V (TCNTV)
181
Table 11.1 Pin Configuration
181
Time Constant Registers a and B (TCORA, TCORB)
182
Timer Control Register V0 (TCRV0)
182
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
183
Timer Control/Status Register V (TCSRV)
184
Timer Control Register V1 (TCRV1)
185
Operation
186
Timer V Operation
186
Figure 11.2 Increment Timing with Internal Clock
187
Figure 11.3 Increment Timing with External Clock
187
Figure 11.4 OVF Set Timing
187
Figure 11.5 CMFA and CMFB Set Timing
188
Figure 11.6 TMOV Output Timing
188
Figure 11.7 Clear Timing by Compare Match
188
Timer V Application Examples
189
Pulse Output with Arbitrary Duty Cycle
189
Figure 11.8 Clear Timing by TMRIV Input
189
Figure 11.9 Pulse Output Example
189
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
190
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
190
Usage Notes
191
Figure 11.11 Contention between TCNTV Write and Clear
191
Figure 11.12 Contention between TCORA Write and Compare Match
192
Figure 11.13 Internal Clock Switching and TCNTV Operation
192
Section 12 Timer W
193
Features
193
Table 12.1 Timer W Functions
194
Figure 12.1 Timer W Block Diagram
195
Input/Output Pins
196
Register Descriptions
196
Table 12.2 Pin Configuration
196
Timer Mode Register W (TMRW)
197
Timer Control Register W (TCRW)
198
Timer Interrupt Enable Register W (TIERW)
199
Timer Status Register W (TSRW)
200
Timer I/O Control Register 0 (TIOR0)
201
Timer I/O Control Register 1 (TIOR1)
203
Timer Counter (TCNT)
204
General Registers a to D (GRA to GRD)
205
Operation
206
Normal Operation
206
Figure 12.2 Free-Running Counter Operation
206
Figure 12.3 Periodic Counter Operation
207
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)
207
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1)
208
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)
208
Figure 12.7 Input Capture Operating Example
209
Figure 12.8 Buffer Operation Example (Input Capture)
210
PWM Operation
211
Figure 12.9 PWM Mode Example (1)
211
Figure 12.10 PWM Mode Example (2)
212
Figure 12.11 Buffer Operation Example (Output Compare)
213
Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: Initial Output Values Are Set to 0)
214
Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: Initial Output Values Are Set to 1)
215
Operation Timing
216
TCNT Count Timing
216
Output Compare Output Timing
216
Figure 12.14 Count Timing for Internal Clock Source
216
Figure 12.15 Count Timing for External Clock Source
216
Input Capture Timing
217
Figure 12.16 Output Compare Output Timing
217
Figure 12.17 Input Capture Input Signal Timing
217
Timing of Counter Clearing by Compare Match
218
Buffer Operation Timing
218
Figure 12.18 Timing of Counter Clearing by Compare Match
218
Figure 12.19 Buffer Operation Timing (Compare Match)
218
Timing of IMFA to IMFD Flag Setting at Compare Match
219
Figure 12.20 Buffer Operation Timing (Input Capture)
219
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
219
Timing of IMFA to IMFD Setting at Input Capture
220
Timing of Status Flag Clearing
220
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
220
Figure 12.23 Timing of Status Flag Clearing by CPU
220
Usage Notes
221
Figure 12.24 Contention between TCNT Write and Clear
221
Figure 12.25 Internal Clock Switching and TCNT Operation
222
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the same Timing
223
Section 13 Watchdog Timer
225
Features
225
Figure 13.1 Block Diagram of Watchdog Timer
225
Register Descriptions
226
Timer Control/Status Register WD (TCSRWD)
226
Timer Counter WD (TCWD)
227
Timer Mode Register WD (TMWD)
228
Operation
229
Figure 13.2 Watchdog Timer Operation Example
229
Section 14 Serial Communication Interface 3 (SCI3)
231
Features
231
Figure 14.1 Block Diagram of SCI3
232
Input/Output Pins
233
Register Descriptions
233
Table 14.1 Pin Configuration
233
Receive Data Register (RDR)
234
Receive Shift Register (RSR)
234
Transmit Data Register (TDR)
234
Transmit Shift Register (TSR)
234
Serial Mode Register (SMR)
235
Serial Control Register 3 (SCR3)
236
Serial Status Register (SSR)
238
Bit Rate Register (BRR)
240
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
241
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
242
Table 14.3 Maximum Bit Rate for each Frequency (Asynchronous Mode)
243
Table 14.4 Examples of BBR Setting for Various Bit Rates (Clocked Synchronous Mode)
244
Operation in Asynchronous Mode
245
Clock
245
Figure 14.2 Data Format in Asynchronous Communication
245
Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
245
SCI3 Initialization
246
Figure 14.4 Sample SCI3 Initialization Flowchart
246
Data Transmission
247
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
247
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
248
Serial Data Reception
249
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
249
Table 14.5 SSR Status Flags and Receive Data Handling
250
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
251
Figure 14.8 Sample Serial Reception Data Flowchart (2)
252
Operation in Clocked Synchronous Mode
253
Clock
253
Figure 14.9 Data Format in Clocked Synchronous Communication
253
SCI3 Initialization
254
Serial Data Transmission
254
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
255
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
256
Serial Data Reception (Clocked Synchronous Mode)
257
Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode
257
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
258
Simultaneous Serial Data Transmission and Reception
259
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
260
Multiprocessor Communication Function
261
Figure 14.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
262
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart
263
Multiprocessor Serial Data Transmission
263
Multiprocessor Serial Data Reception
264
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
265
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)
266
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
267
Interrupts
268
Usage Notes
268
Break Detection and Processing
268
Table 14.6 SCI3 Interrupt Requests
268
Mark State and Break Sending
269
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
269
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
269
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
270
Section 15 I C Bus Interface 2 (IIC2)
271
Features
271
Figure 15.1 Block Diagram of I
272
Input/Output Pins
273
Figure 15.2 External Circuit Connections of I/O Pins
273
Register Descriptions
274
C Bus Control Register 1 (ICCR1)
274
Table 15.2 Transfer Rate
276
C Bus Control Register 2 (ICCR2)
277
C Bus Mode Register (ICMR)
279
C Bus Interrupt Enable Register (ICIER)
281
C Bus Status Register (ICSR)
283
Slave Address Register (SAR)
285
C Bus Transmit Data Register (ICDRT)
286
C Bus Receive Data Register (ICDRR)
286
C Bus Shift Register (ICDRS)
286
Operation
287
C Bus Format
287
Figure 15.3 I 2 C Bus Formats
287
Figure 15.4 I 2 C Bus Timing
287
Master Transmit Operation
288
Figure 15.5 Master Transmit Mode Operation Timing (1)
289
Figure 15.6 Master Transmit Mode Operation Timing (2)
289
Master Receive Operation
290
Figure 15.7 Master Receive Mode Operation Timing (1)
291
Slave Transmit Operation
292
Figure 15.8 Master Receive Mode Operation Timing (2)
292
Figure 15.9 Slave Transmit Mode Operation Timing (1)
293
Slave Receive Operation
294
Figure 15.10 Slave Transmit Mode Operation Timing (2)
294
Figure 15.11 Slave Receive Mode Operation Timing (1)
295
Figure 15.12 Slave Receive Mode Operation Timing (2)
295
Clocked Synchronous Serial Format
296
Figure 15.13 Clocked Synchronous Serial Transfer Format
296
Figure 15.14 Transmit Mode Operation Timing
297
Noise Canceler
298
Figure 15.15 Receive Mode Operation Timing
298
Figure 15.16 Block Diagram of Noise Conceler
298
Example of Use
299
Figure 15.17 Sample Flowchart for Master Transmit Mode
299
Figure 15.18 Sample Flowchart for Master Receive Mode
300
Figure 15.19 Sample Flowchart for Slave Transmit Mode
301
Figure 15.20 Sample Flowchart for Slave Receive Mode
302
Interrupt Request
303
Bit Synchronous Circuit
303
Table 15.3 Interrupt Requests
303
Usage Notes
304
Issue (Retransmission) of Start/Stop Conditions
304
WAIT Setting in I
304
C Bus Mode Register (ICMR)
304
Figure 15.21 the Timing of the Bit Synchronous Circuit
304
Table 15.4 Time for Monitoring SCL
304
Section 16 A/D Converter
305
Features
305
Figure 16.1 Block Diagram of A/D Converter
306
Input/Output Pins
307
Table 16.1 Pin Configuration
307
Register Descriptions
308
A/D Data Registers a to D (ADDRA to ADDRD)
308
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
308
A/D Control/Status Register (ADCSR)
309
A/D Control Register (ADCR)
311
Operation
312
Single Mode
312
Scan Mode
312
Input Sampling and A/D Conversion Time
313
Figure 16.2 A/D Conversion Timing
313
External Trigger Input Timing
314
Figure 16.3 External Trigger Input Timing
314
Table 16.3 A/D Conversion Time (Single Mode)
314
A/D Conversion Accuracy Definitions
315
Figure 16.4 A/D Conversion Accuracy Definitions (1)
316
Figure 16.5 A/D Conversion Accuracy Definitions (2)
316
Usage Notes
317
Permissible Signal Source Impedance
317
Influences on Absolute Accuracy
317
Figure 16.6 Analog Input Circuit Example
317
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
319
Features
320
Figure 17.1 Block Diagram Around BGR
320
Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
321
Register Descriptions
322
Low-Voltage-Detection Control Register (LVDCR)
322
Low-Voltage-Detection Status Register (LVDSR)
323
Table 17.1 LVDCR Settings and Select Functions
323
Reset Source Decision Register (LVDRF)
324
Operations
325
Power-On Reset Circuit
325
Low-Voltage Detection Circuit
326
Figure 17.3 Operational Timing of Power-On Reset Circuit
326
Figure 17.4 Operating Timing of LVDR Circuit
327
Figure 17.5 Operational Timing of LVDI Circuit
328
Deciding Reset Source
329
Figure 17.6 Timing of Setting Bits in Reset Source Decision Register
329
Table 17.2 Deciding Reset Source
329
Section 18 Power Supply Circuit
331
When Using Internal Power Supply Step-Down Circuit
331
Figure 18.1 Power Supply Connection When Internal Step-Down Circuit Is Used
331
When Not Using Internal Power Supply Step-Down Circuit
332
Figure 18.2 Power Supply Connection When Internal Step-Down Circuit Is Not Used
332
Section 19 List of Registers
333
Register Addresses (Address Order)
334
Register Bits
339
Registers States in each Operating Mode
343
Section 20 Electrical Characteristics
347
Absolute Maximum Ratings
347
Electrical Characteristics
347
Power Supply Voltage and Operating Ranges
347
Table 20.1 Absolute Maximum Ratings
347
DC Characteristics
350
Table 20.2 DC Characteristics (1)
350
Table 20.2 DC Characteristics (2)
354
AC Characteristics
355
Table 20.3 AC Characteristics
355
Table 20.4 I 2 C Bus Interface Timing
358
Table 20.5 Serial Communication Interface (SCI) Timing
359
A/D Converter Characteristics
360
Table 20.6 A/D Converter Characteristics
360
Watchdog Timer Characteristics
361
Table 20.7 Watchdog Timer Characteristics
361
Flash Memory Characteristics
362
Table 20.8 Flash Memory Characteristics
362
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
364
Power-On Reset Circuit Characteristics (Optional)
364
Table 20.9 Power-Supply-Voltage Detection Circuit Characteristics
364
Table 20.10 Power-On Reset Circuit Characteristics
364
Operation Timing
365
Figure 20.1 System Clock Input Timing
365
Figure 20.2 RES Low Width Timing
365
Figure 20.3 Input Timing
365
Figure 20.4 I C Bus Interface Input/Output Timing
366
Figure 20.5 SCK3 Input Clock Timing
366
Output Load Condition
367
Figure 20.6 SCI Input/Output Timing in Clocked Synchronous Mode
367
Figure 20.7 Output Load Circuit
367
Appendix A Instruction Set
369
Instruction List
369
Table A.1 Instruction Set
371
Operation Code Map
384
Table A.2 Operation Code Map (1)
384
Table A.2 Operation Code Map (2)
385
Table A.2 Operation Code Map (3)
386
Number of Execution States
387
Table A.3 Number of Cycles in each Instruction
388
Table A.4 Number of Cycles in each Instruction
389
Combinations of Instructions and Addressing Modes
398
Table A.5 Combinations of Instructions and Addressing Modes
398
Appendix B I/O Port Block Diagrams
399
I/O Port Block Diagrams
399
Figure B.1 Port 1 Block Diagram (P17)
399
Figure B.2 Port 1 Block Diagram (P16 to P14)
400
Figure B.3 Port 1 Block Diagram (P12, P11)
401
Figure B.4 Port 1 Block Diagram (P10)
402
Figure B.5 Port 2 Block Diagram (P22)
403
Figure B.6 Port 2 Block Diagram (P21)
404
Figure B.7 Port 2 Block Diagram (P20)
405
Figure B.8 Port 5 Block Diagram (P57, P56)
406
Figure B.9 Port 5 Block Diagram (P55)
407
Figure B.10 Port 5 Block Diagram (P54 to P50)
408
Figure B.11 Port 7 Block Diagram (P76)
409
Figure B.12 Port 7 Block Diagram (P75)
410
Figure B.13 Port 7 Block Diagram (P74)
411
Figure B.14 Port 8 Block Diagram (P87 to P85)
412
Figure B.15 Port 8 Block Diagram (P84 to P81)
413
Figure B.16 Port 8 Block Diagram (P80)
414
Figure B.17 Port B Block Diagram (PB7 to PB0)
415
Figure B.18 Port C Block Diagram (PC1)
416
Figure B.19 Port C Block Diagram (PC0)
417
Port States in each Operating State
418
Appendix C Product Code Lineup
419
Appendix D Package Dimensions
420
Figure D.1 FP-64K Package Dimensions
421
Figure D.2 FP-64A Package Dimensions
422
Figure D.3 FP-48F Package Dimensions
423
Figure D.4 FP-48B Package Dimensions
424
Figure D.5 TNP-48 Package Dimensions
425
Appendix E Function Comparison
426
Index
427
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