Figure 7-29 4-Bit Single Color Passive Lcd Panel A.c.timing; Table 7-25 4-Bit Single Color Passive Lcd Panel A.c.timing - Epson S1D13505F00A Technical Manual

7: A.C. CHARACTERISTICS
Sync Timing
FPFRAME
FPLINE
MOD
Data Timing
FPLINE
FPSHIFT
UD[3:0]

Figure 7-29 4-Bit Single Color Passive LCD Panel A.C.Timing

Table 7-25 4-Bit Single Color Passive LCD Panel A.C.Timing

Symbol
t FPFRAME setup to FPLINE pulse trailing edge
1
t FPFRAME hold from FPLINE pulse trailing edge
2
t FPLINE pulse width
3
t FPLINE period
4
t MOD transition to FPLINE pulse trailing edge
5
t FPSHIFT falling edge to FPLINE pulse leading edge
6
t FPLINE pulse trailing edge to FPSHIFT falling edge
7
t FPSHIFT period
8
t FPSHIFT falling edge to FPLINE pulse trailing edge
9
t FPLINE pulse trailing edge to FPSHIFT rising edge
10
t FPSHIFT pulse width high
11
t FPSHIFT pulse width low
12
t UD[3:0], setup to FPSHIFT falling edge
13
t UD[3:0], hold from FPSHIFT falling edge
14
Notes: 1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4
(see REG[19h] bits [1:0])
2. t = t4 - 14Ts
1min min
3. t = [((REG[04h] bits [6:0]) + 1)∗8 + ((REG[05h] bits [4:0]) + 1)∗8] + 33 Ts
4min
4. t = [(((REG[04h] bits [6:0])+1)∗8 + ((REG[05h] bits [4:0]) + 1)∗8)-1] Ts
5min
5. t = [((REG[05h] bits [4:0]) + 1)∗8 - 28] Ts
6min
6. t = [((REG[05h] bits [4:0]) + 1)∗8 - 19] Ts
9min
1-62
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t1
t3
t5
t6
t10
t9
Parameter Min.
note 2
14
9
note 3
1
note 5
t t
+
10
4
note 6
21
2
2
2
2
EPSON
t2
t4
t7 t8
t11 t12
t13 t14
1 2
Typ. Max. Units
Ts (note 1)
Ts
note 4
Ts
11
Ts
Ts
Ts
Ts
Ts
Ts
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)