Table 6-1: Clock Input Requirements For Clki When Clki To Bclk Divide > 1; Figure 6-1: Clock Input Requirements; A.c. Characteristics; Clock Timing - Epson S1D13706 Technical Manual

Epson Research and Development
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6 A.C. Characteristics

6.1 Clock Timing

6.1.1 Input Clocks

Clock Input Waveform
90%
V
IH
V IL
10%
t r
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Symbol
f Input Clock Frequency (CLKI)
OSC
T Input Clock period (CLKI)
OSC
t Input Clock Pulse Width High (CLKI)
PWH
t Input Clock Pulse Width Low (CLKI)
PWL
t Input Clock Fall Time (10% - 90%)
f
t Input Clock Rise Time (10% - 90%)
r
Note
Hardware Functional Specification
Issue Date: 01/11/13
Conditions: HIO V
DD
NIO V
DD
T = -40° C to 85° C
A
T and T
rise
C = 50pF (Bus/MPU Interface)
L
C = 0pF (LCD Panel Interface)
L
t
PWH

Figure 6-1: Clock Input Requirements

Parameter
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, "Internal Clocks" on page
35 for internal clock requirements.
= 2.0V ± 10% and HIO V
= 3.3V ± 10%
for all inputs must be < 5 nsec (10% ~ 90%)
fall
t
PWL
t
f
T OSC
Min
1/f
OSC
4.5
4.5
= 3.3V ± 10%
DD
2.0V 3.3V
Max Min Max
40
1/f
OSC
4.5
4.5
5
5
Page 33
Units
100 MHz
ns
ns
ns
5 ns
5 ns
S1D13706
X31B-A-001-08