Phy-Link Interface Timing - Epson S1R75801F00A Technical Manual

9.4.2 PHY-LINK Interface Timing

9.4.2.1 Output timing
SCLK
Ctl[0:1]
D[0:7]
LReq
9.4.2.2 Input timing
SCLK
Ctl[0:1]
D[0:7]
LReq
Symbol
SCLK rising edge → C, Ctl,
T
211
LReq delay time (Hi-Z → Output starts.)
SCLK rising edge → C, Ctl,
T
212
LReq delay time (Outputting)
SCLK rising edge → C, Ctl,
T
213
LReq delay time (When output ends.)
Symbol
SCLK rising edge → C, Ctl
T
214
set-up time
SCLK rising edge → C, Ctl
T
215
hold time
T
211
T
214
Description
Description
EPSON
T
212
T
212
Unit Min.
ns 1
ns 1
ns 1
Unit Min.
ns 6
ns 0
S1R72803F00A
T
213
Max.
10
10
10
Max.
95