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1. Functions
1.7.3.1.6
RAM_Rd Access
As with synchronous register reading, data is output to the external bus with the read
(asserted for both XCS and XRD) period as the output enable period. For details, refer to
"1.6.5.1 RAM Access (RAM_Rd)."
1.7.3.1.7
Asynchronous Register Access (Writing)
A write pulse is created from the external write signal (XCS, XWRL, H), and the external
bus data is written to the register.
1.7.3.1.8
Asynchronous Register Access (Reading)
As with synchronous register reading, register data is output to the external bus with the read
(asserted for both XCS and XRD) period as the output enable period.
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EPSON
S2R72V18 Technical Manual (Rev.1.00)
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