Lcd Memory Access Cycles - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center

2.1.2 LCD Memory Access Cycles

TCLK
ADD[25:0]
SHB#
LCDCS#
WR#,RD#
D[15:0]
(write)
D[15:0]
(read)
LCDRDY
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 01/02/12
Figure 2-1: "NEC VR4102 Read/Write Cycles," on page 9 shows the read and write cycles
to the LCD Controller Interface.
Once an address in the LCD block of memory is placed on the external address bus,
ADD[25:0], the LCD chip select, LCDCS#, is driven low. The read or write enable signals,
RD# and WR#, are driven low for the appropriate cycle and LCDRDY is driven low to
insert wait states into the cycle. The high byte enable is driven low for 16-bit transfers and
high for 8-bit transfers.
Hi-Z
Figure 2-1: NEC VR4102 Read/Write Cycles
VALID
*
VALID
Hi-Z
VALID
S1D13704
X26A-G-008-05
Page 9