Figure 3-3 Typical System Diagram (Mc68K Bus 1, 16-Bit 68000, 256Kx16 Fpm/Edo-Dram); Figure 3-4 Typical System Diagram (Mc68K Bus 2, 32-Bit 68030, 256Kx16 Fpm/Edo-Dram) - Epson S1D13505F00A Technical Manual

MC68000
BUS
A[23:21]
Decoder
FC0, FC1
Decoder
A[20:1]
D[15:0]
LDS#
UDS#
AS#
R/W#
DTACK#
BCLK
RESET#

Figure 3-3 Typical System Diagram (MC68K Bus 1, 16-Bit 68000, 256Kx16 FPM/EDO-DRAM)

MC68030
BUS
A[31:21]
Decoder
FC0, FC1
Decoder
A[20:0]
D[31:16]
DS#
AS#
R/W#
SIZ1
SIZ0
DSACK1#
BCLK
RESET#

Figure 3-4 Typical System Diagram (MC68K Bus 2, 32-Bit 68030, 256Kx16 FPM/EDO-DRAM)

S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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3: TYPICAL SYSTEM IMPLEMENTATION DIAGRAMS
Power Oscillator
Management
M/R#
FPDAT[15:8]
FPDAT[7:0]
CS#
FPSHIFT
AB[20:1]
FPFRAME
DB[15:0]
FPLINE
DRDY
S1D13505F00A
AB0#
WE1#
LCDPWR
BS#
RED,GREEN,BLUE
RD/WR#
WAIT# HRTC
VRTC
BUSCLK
RESET# IREF
256Kx16
FPM/EDO-DRAM
Power
Oscillator
Management
M/R#
FPDAT[15:8]
FPDAT[7:0]
CS#
FPSHIFT
AB[20:0]
FPFRAME
DB[15:0]
FPLINE
DRDY
WE1#
BS#
S1D13505F00A
RD/WR# LCDPWR
RD#
RED,GREEN,BLUE
WE0#
HRTC
WAIT#
VRTC
BUSCLK
IREF
RESET#
256Kx16
FPM/EDO-DRAM
EPSON
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
FPFRAME Display
FPLINE
MOD
CRT
Display
IREF
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
FPFRAME Display
FPLINE
MOD
CRT
Display
IREF
1-5