Figure 3-2: Typical System Diagram - Mc68K Bus 1, 1Mx16 Fpm/Edo-Dram (16-Bit Mc68000); Figure 3-3: Typical System Diagram - Mc68K Bus 2, 256Kx16 Fpm/Edo-Dram (32-Bit Mc68030) - Epson S1D13504 Technical Manual

Epson Research and Development
Vancouver Design Center
MC68000
BUS
A[23:21]
FC0, FC1
A[20:1]
D[15:0]
LDS#
UDS#
AS#
R/W#
DTACK#
BCLK
RESET#
Figure 3-2: Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
MC68030
BUS
A[31:21]
FC0, FC1
A[20:0]
D[31:16]
DS#
AS#
R/W#
SIZ1
SIZ0
DSACK1#
BCLK
RESET#
Figure 3-3: Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
Hardware Functional Specification
Issue Date: 01/01/30
Power
Management
M/R#
Decoder
CS#
Decoder
AB[20:1]
DB[15:0]
S1D13504
AB0#
WE1#
BS#
RD/WR#
WAIT#
BUSCLK
RESET#
Power
Management
M/R#
Decoder
CS#
Decoder
AB[20:0]
DB[15:0]
WE1#
S1D13504
BS#
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#
.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
1Mx16
FPM/EDO-DRAM
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
256Kx16
FPM/EDO-DRAM
Page 15
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
Display
FPFRAME
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
Display
FPFRAME
FPLINE
MOD
S1D13504
X19A-A-002-18