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8 Registers
8.1 Register Mapping
CS#
0
0
1
8.2 Register Descriptions
8.2.1 Revision Code Register
Revision Code Register
REG[00h]
Product Code
Product Code
Bit 5
Bit 4
bits 7-2
bits 1-0
S1D13504
X19A-A-002-18
The S1D13504 registers are all memory mapped. The system must provide the external address
decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are
mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is
mapped to AB[5:0] = 000001. See the table below:
Table 8-1: S1D13504 Addressing
M/R#
Register access:
• REG[00h] is addressed when AB[5:0] = 0
0
• REG[01h] is addressed when AB[5:0] = 1
• REG[n] is addressed when AB[5:0] = n
Memory access: the 2M byte display buffer is addressed by
1
AB[20:0]
X
S1D13504 not selected
Note
Unless specified otherwise, all register bits are reset to 0 during power up. Reserved bits should
be written 0 when programming unless otherwise noted.
Product Code
Product Code
Bit 3
Bit 2
Product Code Bits [5:0]
This is a read-only register that indicates the product code of the chip. The product code is 000001.
Revision Code Bits [1:0]
This is a read-only register that indicates the revision code of the chip. The revision code is 00.
Access
Product Code
Product Code
Bit 1
Bit 0
Epson Research and Development
Vancouver Design Center
Revision
Revision
Code Bit 1
Code Bit 0
Hardware Functional Specification
Issue Date: 01/01/30
RO
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