Table 13-4: Power Save Mode Function Summary - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center
13.3 Power Save Mode Function Summary
Note
13.4 Panel Power Up/Down Sequence
Hardware Functional Specification
Issue Date: 01/02/08

Table 13-4: Power Save Mode Function Summary

IO Access Possible?
Memory Access Possible?
Sequence Controller Running?
Display Active?
LCDPWR
FPDAT[11:0], FPSHIFT (see note)
FPLINE, FPFRAME, DRDY
When FPDAT[11:8] are designated as GPIO outputs, the output state prior to enabling
the Power Save Mode is maintained. When FPDAT[11:8] are designated as GPIO in-
puts, unused inputs must be tied to either IO V
face Pin Mapping," on page 23.
After chip reset or when entering/exiting a power save mode, the Panel Interface signals
follow a power on/off sequence shown below. This sequence is essential to prevent damage
to the LCD panel.
Hardware Software
Power Save Power Save
No Yes
No Yes
No No
No No
Inactive Inactive
Forced Low Forced Low
Forced Low Forced Low
or GND - see Table 5-3: "LCD Inter-
DD
*
Page 85
Normal
Yes
Yes
Yes
Yes
Active
Active
Active
S1D13704
X26A-A-001-04