ABB RET670 Applications Manual page 221

1MRK504116-UUS C
Application manual
With bypassed
Source voltage
Source
X
S
~
I
F
ANSI06000605 V1 EN
Figure 84: Voltage inversion on series compensated line
With bypassed
capacitor
I
F
ANSI06000606 V1 EN
Figure 85: Phasor diagrams of currents and voltages for the bypassed and
inserted series capacitor during voltage inversion
It is obvious that voltage V
situation corresponds, from the directionality point of view, to fault conditions on line
without series capacitor. Voltage V
when:
< < +
X X X X
L1 C S L1
EQUATION1902 V1 EN
Where
X is the source impedance behind the IED
S
With inserted
capacitor capacitor
V'
M
V
M
V
X
L1
X
F
X
C
21
en06000605_ansi.vsd
With inserted
capacitor
en06000606_ansi.vsd
will lead the fault current I
M
in IED point will lag the fault current I
M
Section 3
IED application
Pre -fault voltage
Fault voltage
I
F
as long as X > X
F L1
. This
C
in case
F
(Equation 127)
215