Dma Controller; Registers - Universe Control And Status Registers (Ucsr) - Motorola MVME2600 Series Reference Manual

DMA Controller

The Universe provides an internal DMA controller for high performance
data transfer between the PCI and VMEbus. DMA operations between the
source and destination bus are decoupled through the use of a single
bidirectional FIFO (DMAFIFO). Parameters for the DMA transfer are
software configurable in the Universe registers. (Refer to DMA Controller
in the Universe User Manual.)
The principal mechanism for DMA transfers is the same for operations in
either direction (PCI to VME, or VME to PCI), only the relative identity
of the source and destination bus changes. In a DMA transfer, the Universe
gains control of the source bus and reads data into its DMAFIFO.
Following specific rules of DMAFIFO operation (refer to FIFO Operation
and Bus Ownership in the Universe User Manual), it then acquires the
destination bus and writes data from its DMAFIFO.
The DMA controller can be programmed to perform multiple blocks of
transfers using entries in a linked list. The DMA will work through the
transfers in the linked-list following pointers at the end of each linked-list
entry. Linked-list operation is initiated through a pointer in an internal
Universe register, but the linked list itself resides in PCI bus memory.
Registers - Universe Control and Status
Registers (UCSR)
The Universe Control and Status Registers (UCSR) facilitate host system
configuration and allow the user to control Universe operational
characteristics. The UCSRs are divided into three groups:
PCI Configuration Space (PCICS)
VMEbus Control and Status Registers (VCSR), and
Universe Device Specific Status Registers (UDSR)
The Universe registers are little-endian.

Registers - Universe Control and Status Registers (UCSR)

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