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Functional Description
FPGA Access, Watchdog and ENUM registers
The LM78 and the FPGA's watchdog timer is addressed through the
Programmable Chip Select in the South Bridge. The PCS is set to a default
address of 0050h by the BIOS. This can be changed at any time by an
application program if this becomes a conflict. In most cases, the application
4
program will read the PCS register to determine the base address.
To read the PCR register, do a configuration read from the PIIX3 South Bridge
Device 07h, Function 00h, register 78h and 79h.
The watchdog timer and ENUM registers are accessed via three I/O offsets:
0Bh, 0Dh, and 0Fh. The LM78 is accessed through port offsets 00h to 07h. The
following sections describe the function of these registers.
Port offset 0Bh: board status and watchdog strobe
An ISA write to I/O offset 0Bh will reset the watchdog timer to the value of the
watchdog delay programmed into the watchdog register.
Bit
7
Function
Bit
7
Function
Bit 2, the watchdog flag bit, is set by the watchdog Timer when the timer
reaches zero. This can only be reset by clearing the watchdog timer via the
watchdog register.
4-18
Table 4-10. I/O offset 0Bh (write)
6
5
Table 4-11. I/O offset 0Bh (read)
6
5
4
Hardware version number
4
3
2
Do not care
3
2
Reserved
Watchdog
flag
1
0
1
0
Reserved
Reserved
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