Falcon Registers; Falcon-Controlled System Registers; Table 1-13. System Register Summary - Motorola MTX Series Programmer's Reference Manual

Board Description and Memory Maps
1

Falcon Registers

Falcon-Controlled System Registers

BIT # ---->
FEF80400
FEF80404
FEF88000
FEF88100
FEF88200
FEF88300
1-16
The base address of the Falcon chipset's Registers is hard coded to the
address $FEF80000. Accesses to these registers are mapped differently
depending on whether they are read or write operations. For reads, the data
read on the upper half of the data bus comes from the upper Falcon, while
the data read on the lower half of the data bus comes from the lower
Falcon. For writes, internal register or test SRAM data written on the
upperhalf of the data bus goes to the upper Falcon and is automatically
copied by hardware to the lower Falcon. Internal register or test SRAM
data written on the lower half of the data bus does not go to either Falcon
in the pair, however the access is terminated normally with TA#.
The Falcon chipset latches the states of the DRAM data lines onto the
PR_STAT1 and PR_STAT2 registers. The MTX series uses these status
registers to provide the system configuration information. In addition, the
Falcon chipset performs the decode and control for an external register
port. This function is used by the MTX series to provide the system control
registers.

Table 1-13. System Register Summary

System Configuration Register (Upper Falcon's PR_STAT1)
Memory Configuration Register (Lower Falcon's PR_STAT1)
System External
Cache Control
Register
Processor 0
External Cache
Control Register
Processor 1
External Cache
Control Register
CPU Control
Register
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