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WinBIOS Setup
NA Disable (NAD) for external cache
When this option is enabled, the next address pin of the TXC is asserted to
enable CPU pipelining. This option should be enabled. If this option is
disabled, the CPU will not enable memory read/write pipeline modes, this will
slow CPV5000 memory performance significantly.
Extended cachebility
This option should be enabled if the total system DRAM is greater than 64 MB.
The 512K cache module is capable of supporting memory configurations up to
256 MB.
ECC test enable
This option enables the ECC test mode. This ECC mode can detect and correct
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a single bit error, detect double bit errors, and detect all errors confined to a
single nibble. When this mode is enabled, all DRAM leadoff latencies are
increased by one cycle.
DRAM data integrity mode
The DRAM data integrity mode has three options:
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• Disable
When this option is enabled, no checks are performed for parity or ECC.
• Parity
This option enables byte level parity checking. Parity checking only
functions correctly when 36-bit DRAM SIMMs are used. A parity error
asserts SERR#.
• ECC Level 1
This option asserts SERR# when an uncorrectable error is detected. This
results in a system halt. Only single bit errors are correctable. The
corrected data is transferred to the requester (CPU or PCI). The
corrected data is not written to DRAM.
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