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SUPPORT MATERIAL
To provide further information, the following documents are included:
1.
Schematic diagram of '192/202EVK.
2.
Separate Bill of Materials for each board.
3.
Parts layout diagram.
4.
Mechanical drawing of board.
5.
MC145192 and MC145202 data sheets.
6.
Printer port diagram.
7.
Typical signal plots for each type of EVK.
PRODUCTION TEST
After assembly is complete, the following alignment and test is performed on '192EVK (or '202EVK):
1.
The control program is started in single board '190EVK ('200EVK) mode.
2.
L menu item is selected.
3.
Power is applied to the board. DIP switch section 1 is closed circuit with all others being open
circuit.
4.
After attaching computer cable, menu item I is selected.
5.
Trim resistor VR1 is adjusted to obtain an output frequency at J8 of 740.999 – 741.001 MHz
(1481.998 – 1482.002 MHz).
6.
Voltage at the control voltage test point is measured. It must be 2.5 – 3.1 V.
7.
When testing more than 1 board, steps 3 – 6 are repeated.
If in step 5 it isn't possible to obtain a signal on frequency, menu item P should be selected and the cor-
rect printer port address entered. Menu item I would then be selected to reload the data.
BOARD OPERATION
A computer is connected to the DB–25 connector J5. Data is output from the printer port. The printer card
is in slot 0 using the default address in the control program. Data is sent to the PLL device (U1) through
the DIP switch (S1), and 74HCT241 buffer (U5). D2, D3, D4, R19, R20, and R21 are in the data path
between the 74HCT241 and PLL devices. This limits the high level output voltage of the buffer. Voltage
on the PLL device inputs must not be greater than 0.5 V above V CC . A '192/202 PLL has three output
lines which are routed through a 74LS126 line driver (U2) to the computer.
U5, the 74HCT241, provides isolation, logic translation and a turn–on delay for PLL input lines. Logic
translation is needed from the TTL levels on the printer port to the CMOS levels on the '192/202 inputs.
Turn–on delay is used to ensure the power–on reset functions properly. The enable line to the PLL must
be held low during power–up.
A 12 V power supply should be used to power the board at J6 (Augat 2SV–02 connector). The 2SV–02
will accept 18–24 AWG bare copper power leads. No tools are needed for connection. If power is proper-
ly connected, LED D2 will be lit.
Power passes from J6 to U3 (LM317 regulator) configured as an 8.5 V regulator. Both boards use 8.5 V
to power the VCO and RF amplifier. Regulators U4 and U7 use the 8.5 V supply to produce 3 V and 5 V.
The '192 always uses 3 V to power logic and 5 V to power the charge pump, while the '202 can have
either power both the logic and charge pump. J3 and J4 are jumpers which select voltages for the logic
and charge pump supplies. U4 and U7 are cascaded with U3 to equalize their individual voltage drops.
The PLL loop is composed of the PLL device (U1), 733 – 743 MHz VCO (M1), passive loop filter (R11,
R12, C4, C5, C6) and second harmonic filter amplifier (U6). A passive loop filter was used to keep the
MC145192EVK MC145202EVK
4
MOTOROLA
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