Mpc Error Enable Register - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2

MPC Error Enable Register

Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
2-30
where Clk is the frequency of the CLK input in MHz. The
following table shows the scale factors for some common
CLK frequencies.
Frequency
1 1 1
0 1 2
R R
$00 $00
DFLT Default MPC Master ID. This bit determines which
MCHK* pin will be asserted for error conditions in which
the MPC master ID can not be determined or the Raven
was the MPC master. For example, in event of a PCI
parity error for a transaction in which the Raven's PCI
master was not involved, the MPC master ID can not be
determined. When DFLT is set, MCHK1* is used. When
DFLT is clear, MCHK0* will be used.
PADJ
66 $B4
50 $CE
40 $D8
33 $DF
25 $E7
$FEFF0020
1 1 1 1 1 1 1 2 2 2
3 4 5 6 7 8 9 0 1 2
MEREN
2 2 2 2 2 2 2 3 3
3 4 5 6 7 8 9 0 1