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Interrupt Map
External Interrupt Sources
6 - 8
Table 29: System Controller MPP Configuration (cont.)
MPP
Function
[8]
GNT0[4]#
[7]
REQ1[3]#
[6]
GNT1[3]#
[5]
REQ1[2]#
[4]
GNT1[2]#
[3]
REQ1[1]#
[2]
GNT1[1]#
[1]
REQ1[0]#
[0]
GNT1[0]#
The following GPP pins of the system controller are used to connect exter-
nal interrupts to the internal interrupt controller. For a correct functionality,
the GPP pins must be configured according to "System Controller MPP
Configuration" page 6-7.
Table 30: External Interrupt Sources
GPP
Interrupt
[31]
PCI1_INTD#
[30]
PCI1_INTC#
[29]
PCI1_INTB#
[28]
PCI1_INTA#
[27]
PCI0_INTD#
[26]
PCI0_INTC#
[25]
PCI0_INTB#
[24]
PCI0_INTA#
[23]
WDNMI#
[21]
IPMI_IRQ2
[20]
IPMI_IRQ1
[19]
IPMI_IRQ0
Description
PCI bus 0 GNT#
PCI bus 1 REQ#
PCI bus 1 GNT#
PCI bus 1 REQ#
PCI bus 1 GNT#
PCI bus 1 REQ#
PCI bus 1 GNT#
PCI bus 1 REQ#
PCI bus 1 GNT#
Description
Shared PCI interrupts
from PCI bus 1
Shared PCI interrupts
from PCI bus 0
NMI# interrupt from sys-
tem controller's internal
watchdog
Interrupts from the on-
board IPMI controller
Maps and Registers
Direction
Polarity
Output
Active low
Input
Active low
Output
Active low
Input
Active low
Output
Active low
Input
Active low
Output
Active low
Input
Active low
Output
Active low
Source
Polarity
See "PCI Bus 1"
Active low
page 5-12
See "PCI Bus 0"
Active low
page 5-8
Watchdog
Active low
IPMI controller
Active
high
PPC/CPCI-690
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