Programming Notes; External Interrupt Service - Motorola MVME2600 Series Reference Manual

Programming Notes

External Interrupt Service

The following summarizes how an external interrupt is serviced:
1. An external interrupt occurs.
2. The processor state is saved in the machine status save/restore
registers. A new value is loaded into the Machine State Register
(MSR). The External Interrupt Enable bit in the new MSR (MSRee)
is set to zero. Control is transferred to the O/S external interrupt
handler.
3. The external interrupt handler calculates the address of the Interrupt
Acknowledge register for this processor (MPIC Base Address +
0x200A00 + (processor ID shifted left 12 bits)).
4. The external interrupt handler issues an Interrupt Acknowledge
request to read the interrupt vector from the MPIC. If the interrupt
vector indicates the interrupt source is the 8259, the interrupt
handler issues a second Interrupt Acknowledge request to read the
interrupt vector from the 8259. The RavenMPIC does not interact
with the vector fetch from the 8259.
5. The interrupt handler saves the processor state and other interrupt-
specific information in system memory and re-enables for external
interrupts (the MSRee bit is set to 1). RavenMPIC blocks interrupts
from sources with equal or lower priority until an End-of-Interrupt
is received for that interrupt source. Interrupts from higher priority
interrupt sources continue to be enabled. If the interrupt source was
the 8259, the interrupt handler issues an EOI request to the MPIC.
This resets the In-Service bit for the 8259 with in the RavenMPIC
and allows it to recognize higher priority interrupt requests, if any,
from the 8259. If none of the nested interrupt modes of the 8259 are
enabled, the interrupt handler issues an EOI request to the 8259.
Raven Interrupt Controller Implementation
service by the associated processor. The write operation
will update the In-Service register by retiring the highest
priority interrupt. Reading this register returns zeros.
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