Scsi Interrupt Control Register - Motorola MVME172 Programmer's Reference Manual

MC2 Chip
3

SCSI Interrupt Control Register

ADR/SIZ
BIT
NAME
OPER
RESET
3-36
V3 V3 set to a one indicates that the Ethernet interface is not
present. V3 set to a zero indicates that a Ethernet interface
is present.
V4 V4 set to a one indicates that the MC68060 is present. V4
set to a zero indicates that an MC68LC060 is present.
V5 Reserved for internal use only.
V6 V6 = 0 indicates the board is an MVME172FX model
(P2 I/O and 4 IndustryPack connector pairs).
V6 = 1 indicates the board is an MVME172LX model
(front panel I/O and 2 IndustryPack connector pairs).
V7 Reserved for internal use only.
7 6 5
INT
R R R
0 0 R
IL2-IL0 Interrupt Level. These three bits select the interrupt level
for the SCSI processor. Level 0 does not generate an
interrupt.
IEN Interrupt Enable. When this bit is set high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
INT Interrupt Status. This status bit reflects the state of the INT
pin from the SCSI processor (qualified by the IEN bit).
When this bit is high, a SCSI processor interrupt is being
generated at the level programmed in IL2-IL0. This status
bit does not need to be cleared, because it is level
sensitive.
$FFF4202C (8 bits)
4 3
IEN
R/W R R/W
0 PL 0 0 PL
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2 1 0
IL2 IL1 IL0
R/W R/W
0 PL 0 PL