Motorola MVME172 Programmer's Reference Manual page 209

Vme embedded controller
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Tick Timer 1 Interrupt Control Register
ADR/SIZ
BIT
7
NAME
OPER
R
RESET
0
IL2-IL0
ICLR
IEN
INT
http://www.mcg.mot.com/literature
$FFF4201B (8 bits)
6
5
4
INT
IEN
R
R
R/W
0
0 PL
0 PL
These three bits select the interrupt level for the tick
timers. Level 0 does not generate an interrupt.
Writing a logic 1 to this bit clears the tick timer interrupt
(i.e., INT bit in this register). This bit is always read as
zero.
When this bit is set high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
When this bit is high a Tick Timer interrupt is being
generated at the level programmed in IL2-IL0 (if
nonzero). This bit is edge-sensitive and can be cleared by
writing a logic 1 into the ICLR control bit.
Programming Model
3
2
1
ICLR
IL2
IL1
C
R/W
R/W
0 PL
0 PL
0 PL
3
0
IL0
R/W
0 PL
3-21

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