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DMA continued
Interrupt Control Register, IP2 chip
Local Bus Address Counter, IP2 chip
4-40
Status Register, IP2 chip
Table Address Counter, IP2 chip
transfers
2-12
DMAC
byte counter
2-61
command packets
2-53
Control Register 1 (bits 0-7)
Control Register 2 (bits 0-7)
Control Register 2 (bits 8-15)
interrupter
2-19
local bus address counter
LTO error
1-53
off-board error
1-53
parity error
1-52
registers
2-53
Status Register
2-64
TEA, cause unidentified
VMEbus address counter
VMEbus error
1-52
VMEbus requester
2-13
documentation
A-1
double bit error (cycle type = burst read or
non-burst read)
double bit error (cycle type = non-burst write)
5-6
double bit error (cycle type = scrub)
DRAM
1-3
DRAM
and SRAM Memory Controller
Registers
3-25
Control Register 3-45,
memory controller, MC2 chip
Parity Error Interrupt Control Register
3-22
performance
3-6
size control bit encoding 3-27,
Space Base Address Register
Space Size Register
http://www.mcg.mot.com/literature
4-35
4-34
4-42
2-56
2-59
2-57
2-60
1-54
2-60
5-5
5-7
5-18
3-5
3-28
3-25
3-26
DRAM/SRAM Options Register
DTACK
2-9
Dummy Register 0
5-16
Dummy Register 1
5-17
DWB pin
2-8
E
ECC
5-4
edge-sensitive interrupters
edge-sensitive interrupts
ending address register 2-27,
EPROM socket
1-3
EPROM/Flash interface
EPROM/Flash sizing
200/300-Series
1-11
400/500-Series
1-13
errata sheets, chip
1-21
Error Address (Bits 15-8)
Error Address (Bits 23-16)
Error Address (Bits 31-24)
Error Address (Bits 7-4)
error conditions
1-50
Error Logger Register
5-31
error logging, ECC
5-7
error reporting
5-5
as a local bus master
as a local bus slave
4-7
IndustryPack
4-8
IP2 chip
4-7
error sources, local
1-48
Error Syndrome Register
Ethernet address
1-44
Ethernet LAN memory map
Ethernet transceiver interface
examples
generating tick timer periodic interrupt
B-1
IP 16-bit memory space
IP 32-bit I/O space
4-50
IP 32-bit memory space
IP 8-bit memory space
IP I/O space
4-49
3-27
2-18
2-75
2-38
3-2
5-33
5-33
5-32
5-33
4-7
5-34
1-38
1-3
4-47
4-48
4-46
IN-3
I
N
D
E
X
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