Table of Contents
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IP ID space
setting up interrupt handler routine
setting up local bus interrupter
using bus timers
extended access cycles 2-34,
F
fair mode, VMEchip2 2-8,
features
IP2 chip
4-1
MC2 chip
MCECC
MVME172
VMEchip2
Flash Access Time Control Register
Flash memory device
Flash/EPROM interface
functional blocks, VMEchip2
functional description
IP2 chip
4-2
MC2 chip
MCECC
MVME172
VMEchip2
G
GCSR
base address registers, programming
2-37
board address
group address
map decoder
programming model
SIG3-0 interrupters
programming
I
GCSR, VMEchip2 2-20,
General Control Registers, IP2 chip
N
general description
D
IP2 chip
4-2
E
MCECC
X
IN-4
4-51
B-2
1-57
2-37
2-14
3-1
5-1
1-3
2-1
3-40
1-3
3-2
2-4
3-2
5-2
1-5
2-4
2-48
2-47
1-47
2-101
2-19
2-103
2-101
4-24
5-2
General Purpose
B-2
I/O pins
2-97
Inputs Register
Readable Jumpers Header
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
general purpose registers
Global Control and Status Registers (GCSR)
2-20,
global reset
2-18
global reset driver
global time-out timer, VMEbus
GPI inputs, addresses
GPI3 jumper 1-13,
group address, GCSR
I
I/O
and ID space accesses, IP
Control Register 1
Control Register 2
Control Register 3
interfaces
map decoders 2-6, 2-37,
memory maps
I/O space
32-bit IP_ab
IP_a
4-49
IACK
cycle
2-19
daisy-chain
daisy-chain driver
ID Register
VMEchip2
ID space, IP
4-51
indivisible cycles, MC68060
Computer Group Literature Center Web Site
3-33
1-5
2-108
2-108
2-109
2-109
2-110
2-110
2-102
2-101
2-18
2-66
1-9
3-34
2-47
4-54
2-97
2-98
2-98
1-3
2-39
1-21
4-50
2-16
2-17
2-105
1-58
Index
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