Cache Coherency; Sources Of Local Berr; Local Bus Time-Out - Motorola MVME172 Programmer's Reference Manual

Board Description and Memory Maps
1

Cache Coherency

Sources of Local BERR*

Local Bus Time-out

1-48
The MC68060 has the ability to watch local bus cycles executed by other
local bus masters such as the SCSI DMA controller, the LAN, the
VMEchip2 DMA controller, the VMEbus to local bus controller, and the
IP DMA controller.
When snooping is enabled, the MPU can invalidate cache entries as
required by the current cycle. The MPU cannot watch VMEbus cycles
which do not access the local bus on the MVME172. Software must ensure
that data shared by multiple processors is kept in memory that is not
cached. The software must also mark all onboard and off-board I/O areas
as cache inhibited and serialized.
A TEA* signal (indicating a bus error) is returned to the local bus master
when a local bus time-out occurs, a DRAM parity error occurs and parity
checking is enabled, or a VME bus error occurs during a VMEbus access.
Note
The 400/500-Series MVME172 models do not contain parity
DRAM.
The devices on the MVME172 that are able to assert a local bus error are
described below.
A Local Bus Time-out occurs whenever a local bus cycle does not
complete within the programmed time (VMEbus bound cycles are not
timed by the local bus timer). If the system is configured properly, this
should only happen if software accesses a nonexistent location within the
onboard address range.
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