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VMEchip2
Watchdog Timer Control Register
2
ADR/SIZ
BIT
NAME
OPER
RESET
2-72
23
22
21
SRST
WDCS
WDCC
S
C
0 PS
0
WDEN
When this bit is high, the watchdog timer is enabled.
When this bit is low, the watchdog timer is not enabled.
WDRSE
When this bit is high, and a watchdog time-out occurs, a
SYSRESET or LRESET is generated. The WDS/L bit in
this register selects the reset. When this bit is low, a
watchdog time-out does not cause a reset.
WDS/L
When this bit is high and the watchdog timer has timed
out and the watchdog reset enable (WDRSE bit in this
register) is high, a SYSRESET signal is generated on the
VMEbus which in turn causes LRESET to be asserted.
When this bit is low and the watchdog timer has timed out
and the watchdog reset enable (WDRSE bit in this
register) is high, an LRESET signal is generated on the
local bus.
WDBFE
When this bit is high and the watchdog timer has timed
out, the VMEchip2 asserts the BRDFAIL signal pin.
When this bit is low, the watchdog timer does not
contribute to the BRDFAIL signal on the VMEchip2.
WDTO
When this status bit is high, a watchdog time-out has
occurred. When this status bit is low, a watchdog time-out
has not occurred. This bit is cleared by writing a one to the
WDCS bit in this register.
WDCC
When this bit is set high, the watchdog counter is reset.
The counter must be reset within the time-out period or a
watchdog time-out occurs.
$FFF40060 (8 bits of 32)
20
19
WDTO WDBFE WDS/L WDRSE WDEN
C
R
R/W
0
0 P
0 PSL
Computer Group Literature Center Web Site
18
17
16
R/W
R/W
R/W
0 PSL
1 PSL
0 PSL
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