Motorola MVME172 Programmer's Reference Manual page 250

IP2 Chip
Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued)
IP2 Chip Base Address = $FFFBC000
Register
Register Name
Offset
DMAC for IndustryPack b, request 0 or for IndustryPack a, request 1. This register set is referred to as DMACb in the text.
$38 DMA_b
STATUS
4
$39 DMA_b INT
CTRL
$3a DMA ENABLE
$3b RESERVED
$3c DMA_b CON-
TROL 1
$3d DMA_b CON-
TROL 2
$3e RESERVED
$3f RESERVED
$40 DMA_b LB
ADDR
$41 DMA_b LB
ADDR
$42 DMA_b LB
ADDR
$43 DMA_b LB
ADDR
$44 DMA_b IP
ADDR
$45 DMA_b IP
ADDR
$46 DMA_b IP
ADDR
$47 DMA_b IP
ADDR
$48 DMA_b BYTE
CNT
$49 DMA_b BYTE
CNT
$4a DMA_b BYTE
CNT
$4b DMA_b BYTE
CNT
$4c DMA_b TBL
ADDR
$4d DMA_b TBL
ADDR
$4e DMA_b TBL
ADDR
$4f DMA_b TBL
ADDR
4-14
D7 D6 D5
0 DLBE 0
0 0 DINT
0 0 0
0 0 0
DHALT 0 DTBL
INTE 0 DMAEI
0 0 0
0 0 0
LBA31 LBA30 LBA29
LBA23 LBA22 LBA21
LBA15 LBA14 LBA13
LBA7 LBA6 LBA5
0 0 0
IPA23 IPA22 IPA21
IPA15 IPA14 IPA13
IPA7 IPA6 IPA5
0 0 0
BCNT23 BCNT22 BCNT21
BCNT15 BCNT14 BCNT13
BCNT7 BCNT6 BCNT5
TA31 TA30 TA29
TA23 TA22 TA21
TA15 TA14 TA13
TA7 TA6 TA5
Register Bit Names
D4 D3 D2
IPEND CHANI TBL
DIEN DICLR DIL2
0 0 0
0 0 0
ADMA WIDTH1 WIDTH0
DMAEO ENTO TOIP
0 0 0
0 0 0
LBA28 LBA27 LBA26
LBA20 LBA19 LBA18
LBA12 LBA11 LBA10
LBA4 LBA3 LBA2
0 0 0
IPA20 IPA19 IPA18
IPA12 IPA11 IPA10
IPA4 IPA3 IPA2
0 0 0
BCNT20 BCNT19 BCNT18
BCNT12 BCNT11 BCNT10
BCNT4 BCNT3 BCNT2
TA28 TA27 TA26
TA20 TA19 TA18
TA12 TA11 TA10
TA4 TA3 TA2
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D1 D0
IPTO DONE
DIL1 DIL0
0 DEN
0 0
A_CH1 XXX
0 0
0 0
0 0
LBA25 LBA24
LBA17 LBA16
LBA9 LBA8
LBA1 LBA0
0 0
IPA17 IPA16
IPA9 IPA8
IPA1 IPA0
0 0
BCNT17 BCNT16
BCNT9 BCN8
BCNT1 BCNT0
TA25 TA24
TA17 TA16
TA9 TA8
TA1 TA0