Vme Access, Local Bus, And Watchdog Time-Out Control Register - Motorola MVME172 Programmer's Reference Manual

VME Access, Local Bus, and Watchdog Time-out Control Register

ADR/SIZ
BIT 15
NAME
OPER
RESET
WDTO
LBTO
VATO
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$FFF4004C (8 bits of 32)
14 13
VATO LBTO
R/W R/W
0 PS 0 PS
These bits define the watchdog time-out period:
Bit Encoding
0
1
2
3
4
5
6
7
These bits define the local bus time-out value. The timer
begins timing when TS is asserted on the local bus. If TA
or TAE is not asserted before the timer times out, a TEA
signal is sent to the local bus. The timer is disabled if the
transfer is bound for the VMEbus.
0 8 s
1 64 s
2 256 s
3 The timer is disabled
These bits define the VMEbus access time-out value.
When a transaction is headed to the VMEbus and the
VMEchip2 is not the current VMEbus master, the access
timer begins timing. If the VMEchip2 has not received
bus mastership before the timer times out and the
transaction is not write posted, a TEA signal is sent to the
local bus. If the transaction is write posted, a write post
error interrupt is sent to the local bus interrupter.
0 64 s
1 1 ms
2 32 ms
3 The timer is disabled
LCSR Programming Model
12 11 10
WDTO
Time-out Bit Encoding
512 s
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
9 8
R/W
0 PS
Time-out
8 128 ms
9 256 ms
10 512 ms
11 1 s
12 4 s
13 16 s
14 32 s
15 64 s
2-67
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