Tick Timer 3 And 4 Control Registers - Motorola MVME172 Programmer's Reference Manual

Vme embedded controller
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MC2 Chip

Tick Timer 3 and 4 Control Registers

3
ADR/SIZ
BIT
NAME
OPER
RESET
ADR/SIZ
BIT
NAME
OPER
RESET
3-24
Tick Timer 4 Control Register
15
14
13
OVF3
OVF2
OVF1
R
R
0 PL
0 PL
0 PL
Tick Timer 3 Control Register
7
6
OVF3
OVF2
OVF1
R
R
0 PL
0 PL
0 PL
CEN
When this bit is high, the counter increments. When this
bit is low, the counter does not increment.
COC
When this bit is high, the counter is reset to zero when it
compares with the compare register. When this bit is low,
the counter is not reset.
COVF
The overflow counter is cleared when a one is written to
this bit.
OVF3-OVF0
These bits are the output of the overflow counter. The
overflow counter is incremented each time the tick timer
sends an interrupt to the local bus interrupter. The
overflow counter can be cleared by writing a one to
COVF.
$FFF4201C (8 bits)
12
11
OVF0
R
R
R
0 PL
0
$FFF4201C (8 bits)
5
4
3
OVF0
R
R
R
0 PL
0
Computer Group Literature Center Web Site
10
9
8
COVF
COC
CEN
C
R/W
R/W
0 PL
0 PL
0 PL
2
1
0
COVF
COC
CEN
C
R/W
R/W
0 PL
0 PL
0 PL

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