Dmac Vmebus Error; Dmac Parity Error - Motorola MVME172 Programmer's Reference Manual

Board Description and Memory Maps
1

DMAC VMEbus Error

DMAC Parity Error

1-52
Status:
Bit 7 of the MPU Status and DMA Interrupt Count Register, (actually in
the DMAC Status Register) at address $FFF40048.
Comments:
The local bus timer timed out. This usually indicates the MPU tried
read or write an address at which there was no resource. Otherwise, it
indicates a hardware problem.
Description:
The DMAC experienced a VMEbus error during an attempted transfer.
MPU Notification:
DMAC interrupt (when enabled).
Status:
The VME bit is set in the DMAC Status Register (address $FFF40048 bit
1).
Comments:
This indicates the DMAC attempted to access a VMEbus address at which
there was no resource or the VMEbus slave returned a BERR signal.
Note
The 400/500-Series MVME172 models do not contain parity
DRAM.
Description:
Parity error while the DMAC was reading DRAM.
MPU Notification:
DMAC interrupt (when enabled).
Status:
The DLPE bit is set in the DMAC Status Register (address $FFF40048 bit
5).
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