Error Address (Bits 31-24) - Motorola MVME172 Programmer's Reference Manual

MCECC
5

Error Address (Bits 31-24)

ADR/SIZ
BIT
NAME
OPER
RESET
5-32
EALT EALT indicates that the last logging of an error occurred
on a DRAM access by an alternate (MI* not asserted)
local bus master.
ESCRB ESCRB indicates the entity that was accessing DRAM at
the last logging of a single or double bit error. If ESCRB
is 1, it indicates that the scrubber was accessing DRAM.
If ESCRB is 0, it indicates that the local MC68060 bus
master was accessing DRAM.
ERD ERD reflects the state of the local bus READ signal pin at
the last logging of a single or double bit error. ERD = 1
corresponds to READ = high and ERD = 0 to READ =
low. ERD is meaningless if ESCRB is set.
ERRLOG When set, ERRLOG indicates that a single or a double bit
error has been logged by this MCECC, and that no more
is logged until it is cleared. The bit can only be set by
logging an error and cleared by writing a one to it. When
ERRLOG is cleared, the MCECC is ready to log a new
error. Note that because hardware duplicates control
register writes to both MCECCs, clearing ERRLOG in
one MCECC clears it in the other. Any available error
information in either MCECC should be recovered before
clearing ERRLOG.
This register reflects the value that was on bits 31-24 of the local MC68060
address bus at the last logging of an error.
1st $FFF43060/2nd $FFF43160 (8-bits)
31 30 29
EA31 EA30 EA29
R R R
0 PLS 0 PLS 0 PLS
28 27 26
EA28 EA27 EA26
R R R
0 PLS 0 PLS 0 PLS
Computer Group Literature Center Web Site
25 24
EA25 EA24
R R
0 PLS 0 PLS