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Board Description and Memory Maps
1
Description of Error Conditions on the MVME172
MPU Parity Error
1-50
Generally, the bus error handler can interrogate the status bits and proceed
with the result. However, an interrupt can happen during the execution of
the bus error handler (before an instruction can write to the status register
to raise the interrupt mask). If the interrupt service routine causes a second
bus error, the status that indicates the source of the first bus error may be
lost. The software must be written to deal with this.
This section list the various error conditions that are reported by the
MVME172 hardware. A subsection heading identifies each type of error
condition. A standard format gives a description of the error, indicates how
notification of the error condition is made, indicates which status
register(s) have information about the error, and concludes with some
comments pertaining to each particular error.
Note
The 400/500_Series MVME172 models do not contain parity
DRAM.
Description:
A DRAM parity error.
MPU Notification:
TEA is asserted during an MPU DRAM access.
Status:
Bit 9 of the MPU Status and DMA Interrupt Count Register in the
VMEchip2 at address $FFF40048.
Comments:
After memory has been initialized, this error normally indicates a
hardware problem.
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