Programming The Tick And Watchdog Timers; Vmebus Arbiter Time-Out Control Register - Motorola MVME172 Programmer's Reference Manual

DLOB
DLPE
DLBE
MLTO

Programming the Tick and Watchdog Timers

The VMEchip2 has two 32-bit tick timers and one watchdog timer. This
section provides addresses and bit level descriptions of the prescaler, tick
timer, watchdog timer registers and various other timer registers.

VMEbus Arbiter Time-out Control Register

ADR/SIZ
BIT 31
NAME
OPER
RESET
This register controls the VMEbus arbiter time-out timer.
ARBTO
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When this bit is set, the DMAC received a TEA and the
status indicated off-board. This bit is cleared when the
DMAC is enabled.
When this bit is set, the DMAC received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared when the DMAC is enabled.
This bit is not defined for MVME172 implementation.
When this bit is set, the DMAC received a TEA and
additional status was not provided. This bit is cleared
when the DMAC is enabled.
When this bit is set, the MPU received a TEA and the
status indicated a local bus time-out. This bit is cleared by
a writing a one to the MCLR bit in this register.
$FFF4004C (8 bits [1 used] of 32)
30 29 28
When this bit is high, the VMEbus grant time-out timer is
enabled. When this bit is low, the VMEbus grant timer is
disabled. When the timer is enabled and the arbiter does
not receive a BBSY signal within 256 s after a grant is
issued, the arbiter asserts BBSY and removes the grant.
The arbiter then rearbitrates any pending requests.
LCSR Programming Model
27 26 25
2
24
ARBTO
R/W
0 PS
2-65