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IPEND
DMA Interrupt Control Register
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
ADR/SIZ
BIT
7
NAME
0
OPER
R
RESET
0 R
DIL2-DIL0
DICLR
DIEN
DINT
DMA Enable Register
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
ADR/SIZ
BIT
7
NAME
0
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When this bit is set, the DMA process was terminated if
the DMAEND signal was asserted by the Industry Pack
and the DMAEI bit is set in the DMA Control Register
2.This bit is cleared when DMA is enabled. A DMAC
interrupt will be generated if interrupts are enabled
$FFFBC021, $39, $51, $69 (8 bits each)
6
5
4
0
DINT
DIEN
R
R
R/W
0 R
1 R
0 R
These three bits select the interrupt level for DMA. Level
0 does not generate an interrupt.
Writing a logic 1 to this bit clears the DINT status bit.
When DIEN is set, the interrupt is enabled. When DIEN
is cleared, the interrupt is disabled.
When this bit is high, an interrupt will be generated for a
DMAC if the DIEN bit is set to a one. The interrupt is at
the level programmed in DL2-DL0. The DINT bit is set
when one of the following bits are set in the Status
Register: DLBE, IPEND, CHANI, IPTO, and DONE.
$FFFBC022, $3A, $52, $6A (8 bits each)
6
5
4
0
0
0
Programming Model
3
2
1
DICLR
DIL2
DIL1
C
R/W
R/W
0 R
0 R
0 R
3
2
1
0
0
0
4
0
DIL0
R/W
0 R
0
DEN
4-35
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