Motorola MVME172 Programmer's Reference Manual page 278

IP2 Chip
ADR/SIZ
BIT
NAME
4
OPER
RESET
ADR/SIZ
BIT
NAME
OPER
RESET
4-42
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
$FFFBC030, $48, $60, $78 (32 bits each)
31...24 23
0
R
DMA Table Address Counter
In the command chaining mode, this counter should be loaded by the
processor with the starting address of the list of commands. Note that the
command packets in local bus memory must always be 16-byte aligned.
That is, the starting address of any command packet must have the least
significant nibble of the address set to a zero. If the Table Address Counter
is initialized with a value where the four least significant bits are not a zero,
the logic will interpret it as a halt condition and the command chaining
process will not start. Therefore the entry in the last command packet
which is loaded into the Table Address Counter should have one or more
of these address bits set to a one to halt the command chaining process.
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
$FFFBC034, $4C, $64, $7C (32 bits each)
31
DMA_a Byte Counter
R/W
0 R
...
DMA Table Address Counter
R/W
0 R
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0
0