Sram Space Base Address Register; Dram Space Size Register - Motorola MVME172 Programmer's Reference Manual

MC2 Chip

SRAM Space Base Address Register

ADR/SIZ
3
BIT
NAME
OPER
RESET

DRAM Space Size Register

ADR/SIZ
BIT
NAME
OPER
RESET
3-26
B31-B17 B31 - B17 are compared to local bus address signals A31
- A17 for memory reference cycles. If they compare, an
SRAM cycle is initiated. Note that the same linkage that
exists between the DRAM Base and Size Registers also
exists for the SRAM decode logic. Refer to the DRAM
Space Base Register description.
31 30 29
R/W R/W R/W
0 PL 0 PL 0 PL
DZ2-DZ0 The size bits configure the non-ECC DRAM decoder for
a particular memory size. The following table defines
their encoding. Note that the table specifies the allowed
bit combinations for DZ2 - DZ0. Any other combinations
generate unpredictable results.
DZ2 - DZ0 are set equal to the DZ2 - DZ0 bits of the
DRAM/SRAM Options Register. Note that changing DZ2
- DZ0 so that the DRAM architecture changes between
interleaved and non-interleaved relocates the data. DZ2 -
DZ0 are programmable to facilitate diagnostic software.
$FFF42020 (16 bits)
15-1
B31-B17
R/W
$FFE0 PL
$FFF42024 (8 bits)
28 27
R/W R/W
0 PL 0 PL
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0
R
26 25 24
DZ2 DZ1 DZ0
R/W R/W R/W
0 PL 0 PL 0 PL