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MC2 Chip
Offset
D31-D24
3
$40
Bus Clock
$44
RESET Switch
Control
$48
DRAM Control
$4C
32-bit Prescaler Count Register
Programming Model
3-10
Table 3-2. MC2 Chip Register Map (Continued)
D23-D16
PROM Access
Time Control
Watchdog Timer
Control
Reserved
This section defines the programming model for the control and status
registers (CSR) in the MC2 chip. The base address of the CSR is
$FFF42000. The possible operations for each bit in the CSR are as follows:
R
This bit is a read-only status bit.
R/W
This bit is readable and writable.
C
Writing a one to this bit clears this bit or another bit. This
bit reads zero.
The possible states of the bits after local and power-up reset are as defined
below.
P
The bit is affected by power-up reset.
L
The bit is affected by local reset.
X
The bit is not affected by reset.
0
The bit is always 0.
1
The bit is always 1.
D15-D8
Flash Access Time
Control
Access &
Watchdog Time
Base Select
MPU Status
Computer Group Literature Center Web Site
D7-D0
ABORT Switch
Interrupt Control
Reserved
Reserved
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