Chip Id Register; Chip Revision Register - Motorola MVME172 Programmer's Reference Manual

Table 4-3. IP2 Chip Memory Map - Control and Status Registers (Continued)
IP2 Chip Base Address = $FFFBC000
Register
Register Name
Offset
$80 Programmable
Clock INT CON-
TROL
$81 Programmable
Clock GEN
CONTROL
$82 Programmable
Clock TIMER
$83 Programmable
Clock TIMER

Chip ID Register

The read-only Chip ID Register is hard-wired to a hexadecimal value of
$23. Writes to this register do nothing, however the IP2 chip terminates
them normally with TA*.
ADR/SIZ
BIT
7
NAME CID7
OPER
R
RESET
0

Chip Revision Register

The read-only Chip Revision Register is hard-wired to reflect the revision
level of the IP2 chip ASIC. The current value of this register is $01. Writes
to this register do nothing, however the IP2 chip terminates them normally
with TA*.
This register reads zero on some IP2 chips. It should read 1.
!
The workaround for this is to test the MC2 chip Revision
Register.
Caution
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D7 D6 D5
0 IRE INT
PLTY PLS 0
T15 T14 T13
T7 T6 T5
$FFFBC000 (8 bits)
6 5
CID6 CID5
R R
0 1
Register Bit Names
D4 D3 D2
IEN ICLR IL2
EN CLR PS2
T12 T11 T10
T4 T3 T2
4 3 2
CID4 CID3 CID2
R R R
0 0 0
Programming Model
D1 D0
IL1 IL0
PS1 PS0
T9 T8
T1 T0
1 0
CID1 CID0
R R
1 1
4-17
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